a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly relates to a method for manufacturing an integrated circuit (IC) or other such semiconductor device having a MOS transistor.
b) Description of the Related Art
The use of a salicide (self-aligned silicide) process is a known method for manufacturing a MOS transistor with an LDD (Lightly Doped Drain) structure having low-resistance source and drain regions. With this method, the size of the source and drain regions has to be increased in circuit areas that require high resistance, such as input/output protection circuits, and this was disadvantageous in terms of raising the integration of the transistor.
In view of this, methods that improve on the salicide process have been proposed for manufacturing a MOS transistor with an LDD structure having high-resistance source and drain regions (see JP-A-Hei 5-3173, for example). FIGS. 21 to 23 illustrate the steps for manufacturing a MOS transistor having high-resistance source and drain regions and a MOS transistor having low-resistance source and drain regions according to this method.
In the step in FIG. 21, a field insulation film 11 having element holes 11a and 11b is formed on the surface of a p type silicon substrate 10, after which gate insulation films 12a and 12b are formed on the surface of the silicon substrate 10 inside the element holes 11a and 11b. A poly-Si (silicon) layer and a WSi (tungsten silicide) layer are deposited successively on the substrate surface, after which the poly-Si and WSi layers are patterned in the desired gate pattern to form gate electrode layers Ga and Gb over the gate insulation films 12a and 12b, respectively. The gate electrode layer Ga comprises the poly-Si layer 13a and WSi layer 14a remaining after the patterning, and the gate electrode layer Gb comprises the poly-Si layer 13b and WSi layer 14b remaining after the patterning.
Next, the surface of the silicon substrate 10 inside the element holes 11a and 11b is selectively doped with n.sup.- type impurities using the gate insulation film 12a and the gate electrode layer Ga, the gate insulation film 12b and the gate electrode layer Gb, and the field insulation film 11 as masks, which forms an n.sup.- type source region 15s and drain region 15d, and forms an n.sup.- type source region 16s and drain region 16d. A silicon oxide film is deposited on the substrate surface as a side spacer material film, after which this side spacer material film is etched to form side spacers 17s and 17d on both side walls of the gate electrode layer Ga, and to form side spacers 18s and 18d on both side walls of the gate electrode layer Gb. The etching treatment here results in the etching of the portions of the gate insulation films 12a and 12b not covered by the gate electrode layers Ga and Gb and the side spacers 17s, 17d, 18s, and 18d, and in the exposure of the source regions 15s and 16s and drain regions 15d and 16d.
Next, a silicon oxide film is deposited on the substrate surface as an anti-silicide conversion film, after which the anti-silicide conversion film is etched using a resist layer as a mask, which leaves behind an anti-silicide conversion film 19 that covers a first gate component including the gate insulation film 12a, the gate electrode layer Ga, and the side spacers 17s and 17d; a portion Rs of the source region 15s that is adjacent to the first gate component; and a portion Rd of the drain region 15d that is adjacent to the first gate component. After this, a Ti (titanium) film 20 is deposited as a silicide-forming metal film on the substrate surface.
In the step in FIG. 22, after a silicide conversion treatment has been performed, the unreacted portion of the Ti film 20 is removed by etching. As a result, silicide layers 21s, 21d, 22s, and 22d are formed in the source region 15s, the drain region 15d, source region 16s, and the drain region 16d, respectively. No silicide conversion reaction occurs in the WSi layer 14b of the gate electrode layer Gb at this point.
In the step in FIG. 23, the anti-silicide conversion film 19 is removed by etching. The surface of the silicon substrate 10 inside the element holes 11a and 11b is selectively doped with n type impurities via the silicide layers 21s, 21d, 22s, and 22d and using a first gate component including the gate insulation film 12a, the gate electrode layer Ga, and the side spacers 17s and 17d; and a second gate component including the gate insulation film 12b, the gate electrode layer Gb, and the side spacers 18s and 18d; and the field insulation film 11 as masks, which forms an n.sup.+ type source region 23s and drain region 23d, and forms an n.sup.+ type source region 24s and drain region 24d.
With the above manufacturing method, as to the MOS transistor formed inside the element hole 11a, no silicide layer is formed on the portion Rs of the source region 23s directly covered by the anti-silicide conversion film 19, or on the portion Rd of the drain region 23d directly covered by the anti-silicide conversion film 19, and both of these portions Rs and Rd are high-resistance components. Meanwhile, as to the MOS transistor formed inside the element hole 11b, since no anti-silicide conversion film such as the film 19 was positioned in either the source region 24s or the drain region 24d, the silicide layers 22s and 22d account for the majority of the source region 24s and the drain region 24d, which means that the source region 24s and the drain region 24d are both low in resistance.
The MOS transistor inside the element hole 11a has high resistance to electrostatic discharge (ESD), and is used for an IC input/output circuit or the like. The MOS transistor inside the element hole 11b, meanwhile, has low resistance to ESD, and is used for an IC internal circuit or the like. With the above manufacturing method, the location where the anti-silicide conversion film 19 is formed may be somewhat out of position due to misalignment during the formation of the resist layer that serves as the etching mask by photolithography. A problem with this is the large amount of variance in the resistance values of the high- and low-resistance components Rs and Rd.
Also, three more steps are required than in an ordinary salicide process, namely, the deposition, patterning, and removal of the anti-silicide conversion film, which is a problem in terms of a greater number of manufacturing steps.